1. Technical Field
The present invention relates generally to an improved system and method for improving the operational characteristics of a circuit. In particular, the present invention provides a system and method for masking a portion of a circuit while performance improvements are made to other portions of the circuit so that existing circuits may be migrated to new technologies without further modification or redesign.
2. Description of Related Art
In previous semiconductor technologies, technology speed improvements within a general Very Large Scale Integrated (VLSI) circuit fabrication technology scaled well. That is, both N- and P-type transistors increased their current and switching speeds in the VLSI circuits relatively equally. While wiring usually scaled at a different rate than transistor speeds, innovations which increased the speed of either transistors or wiring generally improved the frequency of the integrated circuit designs. In particular, speeds of various types of transistors scaled nearly equally.
In the more recent past, particularly in the 90 nm technology families, improvements to transistor performance have come primarily from improvements in P-type transistor performance while N-type transistors remained roughly constant. This leads to what is called a “beta ratio” shift, i.e. a shift in the relative strength of N-type versus P-type transistors. This in turn leads to several problems.
Since the circuits on a given integrated circuit chip design were optimized for performance and yield for a target technology, they necessarily must assume a nearly constant beta ratio for the design point. Many large processor designs have person-decades or even person-centuries invested into optimizing for highest possible frequency.
For normal digital circuits, the curve of performance versus optimum P-type and N-type transistor sizes is fairly shallow. Thus, most simple digital circuits will speed up somewhat if either the N-type or P-type transistor performance improves. Even if they are not optimized for maximum frequency improvement in the new target technology, they will speed up satisfactorily without expensive design changes or redesign. In fact, gains achievable via redesign are often not economically feasible.
However, many analog and dynamic circuits are not so forgiving. In cases of beta ratio shifts, analog and dynamic circuits can actually stay the same speed or slow down, thus become the limiting factor in frequency improvement. Indeed, they often may become non-functional with beta ratio shifts, thus forcing expensive and time consuming redesign. Often they are fast enough, in the original technology, to already support a reduced cycle time so some method of keeping them unchanged in the new technology is desired.
Therefore, it has become quite important to find ways to ensure the scalability of these critical types of circuits. Current practice and state of the art has not afforded such a method, other than extremely expensive methods of fabricating multiple technologies on a chip, such as bipolar circuits plus Complementary Metal Oxide Semiconductor (CMOS) where the bipolar circuits could be used for analog circuits and be kept the same when the performance of the digital CMOS circuits are improved. However for reasons of manufacturing cost and power efficiency, it is desirable to fabricate all of the analog and digital circuits in the same technology, usually preferably in CMOS.